1. Technical Field
The present invention generally relates to a semiconductor integrated circuit device, and particularly relates to a semiconductor integrated circuit device that is manufactured using a standard cell methodology. Furthermore, the present invention relates to a method for designing the layout of such a semiconductor integrated circuit device.
2. Related Art
In layout design of a standard-cell semiconductor integrated circuit device, placement and routing of circuit elements such as MOS transistors are determined by placing and connecting a plurality of types of standard cells constituting circuit blocks that realize desired functions using a computer. At this time, in order to prevent deterioration of the gate dielectric of a MOS transistor due to the antenna effect, a protective diode is connected between the gate electrode of a predetermined MOS transistor and a power supply line.
The antenna effect is a phenomenon in which in an etching process of a metal interconnect layer of a semiconductor integrated circuit device, an electric charge is accumulated in a long interconnect. For example, during plasma etching of the metal interconnect layer, if the amount of electric charge that is accumulated on a gate electrode connected to a long interconnect increases, an electrical breakdown of a gate dielectric occurs, leading to deterioration of the gate dielectric, which may become a primary factor in the occurrence of a leakage current. Therefore, in the etching process of the metal interconnect layer, when a long interconnect that is connected to the gate electrode of a MOS transistor is formed and this interconnect is not connected to the source or the drain of another MOS transistor, the antenna effect causes a problem.
In order to prevent deterioration of gate dielectrics due to the antenna effect described above, in layout design of a standard-cell semiconductor integrated circuit device of related art, after placement of a plurality of standard cells, protective diodes are preferentially placed in empty regions.
As an example of related art, JP-A-2000-332206 (paragraphs 0015-0017, FIGS. 1 and 2) discloses a semiconductor integrated circuit device that is aimed at reliably preventing breakdown or the like of the gate oxide of a transistor due to the antenna effect without increasing the area of an LSI chip.
In this semiconductor integrated circuit device, a plurality of standard cells corresponding to logic functions are provided, gaps are provided between the standard cells, the gaps serving as unused regions in which no standard cell is provided, and metal interconnects for electrically connecting the standard cells to each other are provided. In a part of the unused regions, protective cells for protecting against the antenna effect are provided between a power supply line and a ground line, input terminals of the protective cells are connected to the metal interconnects, and thus the standard cells are protected from breakdown of gate oxides that is caused by the antenna effect.
However, in manufacturing of a semiconductor integrated circuit device, there are cases where the need to perform circuit modification arises after a photomask to be used to form gate electrodes, impurity diffusion regions, and interconnects on a semiconductor substrate is produced. Furthermore, there also are cases where the need to perform circuit modification arises after the gate electrodes and the impurity diffusion regions are actually formed on the semiconductor substrate. In layout design of standard-cell semiconductor integrated circuit devices of related art, no consideration has been given to a measure for allowing circuit modification to be performed in such cases.